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KM62V256C, KM62U256C Family
CMOS SRAM
32Kx8 bit Low Power & Low Vcc CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION
* Process Technology : 0.7m CMOS * Organization : 32K x 8 * Power Supply Voltage KM62V256C family : 3.3V 0.3V KM62U256C family : 3.0V 0.3V * Low Data Retention Voltage : 2V(Min) * Three state output and TTL Compatible * Package Type : JEDEC Standard 28-SOP, 28-TSOP(I)-Forward/Reverse The KM62V256C and KM62U256C family are fabricated by SAMSUNG's advanced CMOS process technology. The family can support various operating temperature ranges and has various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Product List KM62V256CL-L KM62U256CL-L Operating Temp. Commercial (0~70 C) Vcc Range 3.0~3.6V 2.7~3.3V 3.0~3.6V 2.7~3.3V 3.0~3.6V 2.7~3.3V Speed (ns) 70*/100 85*/100 70*/100 85*/100 70*/100 85*/100 Power Dissipation PKG Type 28-SOP** 28-TSOP(I) R/F 28-SOP** 28-TSOP(I) R/F 28-SOP** 28-TSOP(I) R/F
Standby (Isb1, Max) Operating (Icc2)
10 A 10 A 20 A 15 A 20 A 15 A 35mA
KM62V256CLE-L Extended KM62U256CLE-L (-25~85 C) KM62V256CLI-L KM62U256CLI-L Industrial (-40~85 C)
* measured with 30pF test load ** the device with 100ns SOP package in 3.0~3.6V Vcc range is not produced.
PIN DESCRIPTION
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 Vcc /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 A3 A4 A5 A6 A7 A12 A14 Vcc /WE A13 A8 A9 A11 /OE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A2 A1 A0 IO1 IO2 IO3 Vss IO4 IO5 IO6 IO7 IO8 /CS A10 /OE A11 A9 A8 A13 /WE Vcc A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 /CS IO8 IO7 IO6 IO5 IO4 Vss IO3 IO2 IO1 A0 A1 A2
FUNCTIONAL BLOCK DIAGRAM
A0~2, A9~11
Y-Decoder
A3~A8 A12~14
28-Pin TSOP Type I - Forward
X-Decoder
Control Logic
Cell Array
28-Pin SOP 22
21 20 19 18 17 16 15
I/O1~8
I/O Buffer Function
/CS, /WE /OE
Pin Name A0~A14 /WE /CS /OE I/O1~I/O8 Vcc Vss
28-Pin TSOP Type I - Reverse
Address Inputs Write Enable Input Chip Select Input Output Enable Input Data Input/Output Power Ground
Revision 04 April 1996
-1ELECTRONICS
KM62V256C, KM62U256C Family
PRODUCT LIST & ORDERING INFORMATION
PRODUCT LIST
Commercial Temp Products (0~70 C) Part Name
KM62V256CLG-7L KM62V256CLTG-7L KM62V256CLTG-10L KM62V256CLRG-7L KM62V256CLRG-10L KM62U256CLG-8L KM62U256CLTG-8L KM62U256CLRG-8L KM62U256CLG-10L KM62U256CLTG-10L KM62U256CLRG-10L
CMOS SRAM
Extended Temp Products (-25~85 C) Part Name
KM62V256CLGE-7L KM62V256CLTGE-7L KM62V256CLRGE-7L
Industrial Temp Products (-40~85 C) Part Name
KM62V256CLGI-7L KM62V256CLTGI-7L KM62V256CLTGI-10L KM62V256CLRGI-7L
Function
28-SOP, 70ns, 3.3V 28-TSOP F, 70ns, 3.3V 28-TSOP F, 100ns, 3.3V 28-TSOP R, 70ns, 3.3V
Function
28-SOP, 70ns, 3.3V 28-TSOP F, 70ns, 3.3V 28-TSOP R, 70ns, 3.3V
Function
28-SOP, 70ns, 3.3V 28-TSOP F, 70ns, 3.3V 28-TSOP F, 100ns, 3.3V 28-TSOP R, 70ns, 3.3V
KM62V256CLTGE-10L 28-TSOP F, 100ns, 3.3V
28-TSOP R, 100ns, 3.3V KM62V256CLRGE-10L 28-TSOP R, 100ns, 3.3V KM62V256CLRGI-10L 28-TSOP R, 100ns, 3.3V 28-SOP, 85ns, 3.0V 28-TSOP F, 85ns, 3.0V 28-TSOP R, 85ns, 3.0V 28-SOP, 100ns, 3.0V 28-TSOP F, 100ns, 3.0V KM62U256CLGE-8L KM62U256CLTGE-8L KM62U256CLRGE-8L KM62U256CLGE-10L 28-SOP, 85ns, 3.0V 28-TSOP F, 85ns, 3.0V 28-TSOP R, 85ns, 3.0V 28-SOP, 100ns, 3.0V KM62U256CLGI-8L KM62U256CLTGI-8L KM62U256CLRGI-8L KM62U256CLGI-10L 28-SOP, 85ns, 3.0V 28-TSOP F, 85ns, 3.0V 28-TSOP R, 85ns, 3.0V 28-SOP, 100ns, 3.0V
KM62U256CLTGE-10L 28-TSOP F, 100ns, 3.0V
KM62U256CLTGI-10L 28-TSOP F, 100ns, 3.0V
28-TSOP R, 100ns, 3.0V KM62U256CLRGE-10L 28-TSOP R, 100ns, 3.0V KM62U256CLRGI-10L 28-TSOP R, 100ns, 3.0V
ORDERING INFORMATION K M6 2 X 256 C X X X - XX X
L-Low Low Power, Blank-Low Power or High Power Access Time : 7=70ns, 8=85ns, 10=100ns Operating Temperature : I=Industrial, E=Extended, Blank=Commercial Package Type : G=SOP, TG=TSOP Forward, RG=TSOP Reverse L-Low Power or Low Low Power, Blank-High Power Die Version : C=4th generation Density : 256=256Kbit V=3.0~3.6V, U=2.7~3.3V, Blank=5V Organization : 2= x8 SEC Standard SRAM
-2ELECTRONICS
Revision 04 April 1996
KM62V256C, KM62U256C Family
ABSOLUTE MAXIMUM RATINGS *
Item Voltage on any pin relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol Ratings -0.3 to 4.6 0.7 -65 to 150 0 to 70 -25 to 85 -40 to 85 Soldering temperature and time Tsolder 260 C, 10sec (Lead Only) Unit V V W C C
CMOS SRAM
Remark
KM62V256CL-L, KM62U256CL-L
Vin, Vout -0.5 to Vcc+0.5 Pd Tstg Ta
Voltage on Vcc supply relative to Vss Vcc
C KM62V256CLE-L, KM62U256CLE-L C KM62V256CLI-L, KM62U256CLI-L -
* Stresses greater than those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss Vih Vil Product KM62V256C Family KM62U256C Family All KM62V256C Family KM62U256C Family KM62V256C Family KM62U256C Family
* 1) Commercial Product : Ta=0 to 70 C, unless otherwise specified 2) Extended Product : Ta=-25 to 85 C, unless otherwise specified 3) Industrial Product : Ta=-40 to 85 C, unless otherwise specified ** Ta=25 C *** Vil(min)=-3.0V for A 0ns pulse 3
Min 3.0 2.7 0 2.2 2.2 -0.3 -0.3***
Typ** 3.3 3.0 0 -
Max 3.6 3.3 0 Vcc+0.3 Vcc+0.3 0.4 0.4
Unit V V V V V V V
CAPACITANCE * (f=1MHz, Ta=25 C)
Item Input capacitance Input/Output capacitance Symbol Cin Cio Test Condition Vin=0V Vio=0V Min Max 6 8 Unit pF pF
* Capacitance is sampled not 100% tested
-3ELECTRONICS
Revision 04 April 1996
KM62V256C, KM62U256C Family
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Symbol Ili Ilo Test Conditions 1) Vin=Vss to Vcc /CS=Vih or Vil or /WE=Vil Vio=Vss to Vcc Operating power supply current Icc Average operating current Icc1 /CS=Vil, Vin=Vih or Vil, Iio=0mA Cycle time=1uS 100% duty /CS A .2V, Vil A .2V, 0 0 Vin A cc-0.2V, Iio=0mA V Icc2 Output low voltage Output high voltage Standby Current(TTL) Standby Current (CMOS) KM62V256CL-L KM62V256CLE-L KM62V256CLI-L KM62U256CL-L KM62U256CLE-L KM62U256CLI-L Vol Voh Isb Isb1 Min cycle, 100% duty /CS=Vil, Iio=0mA Iol=2.1mA Ioh=-1.0mA /CS=Vih /CS A cc-0.2V Low Low PWR V Low Low PWR Vin A .2V or 0 Vin A cc-0.2V Low Low PWR V Low Low PWR Low Low PWR Low Low PWR 2.2 1.5 1.5 1.5 1.0 1.0 1.0 20 3) 1.0 2.5 Min -1 -1
CMOS SRAM
Typ 2) -
Max 1 1 2.0 5
Unit uA uA mA mA
354) 0.4 0.3 10 20 20 10 15 15
mA V V mA uA uA uA uA uA uA
1) - Commercial Product : Ta=0 to 70 C , Vcc=3.0 +/- 0.3V(62U256C Family), Vcc=3.3 +/- 0.3V(62V256C Family) - Extended Product : Ta=-25 to 85 C , Vcc=3.0 +/- 0.3V(62U256CE Family), Vcc=3.3 +/- 0.3V(62V256CE Family) - Industrial Product : Ta=-40 to 85 C , Vcc=3.0 +/- 0.3V(62U256CI Family), Vcc=3.3 +/- 0.3V(62V256CI Family) 2) Ta=25 C 3) 25mA for KM62V256C family 4) 30mA for KM62U256C family but it is not 100% tested but obtained statistically
A.C CHARACTERISTICS
TEST CONDITIONS(1. Test Load and Test Input/Output Reference) *
Item Input pulse level Input rise fall time Value 0.4 to 2.2V 5ns Remark * Including scope and jig capacitance
CL*
Input and output reference voltage 1.5V Output load(See right) CL=100pF+1TTL CL=30pF+1TTL
* See test condition of DC and Operating characteristics
-4ELECTRONICS
Revision 04 April 1996
KM62V256C, KM62U256C Family
TEST CONDITIONS (2. Temperature and Vcc Conditions)
Product Family KM62V256CL-L KM62V256CLE-L KM62V256CLI-L KM62U256CL-L KM62U256CLE-L KM62U256CLI-L Temperature 0~70 C -25~85 C -40~85 C 0~70 C -25~85 C -40~85 C Power Supply(Vcc) 3.3V +/- 0.3 3.3V +/- 0.3 3.3V +/- 0.3 3.0V +/- 0.3 3.0V +/- 0.3 3.0V +/- 0.3 Speed Bin 70*/100ns 70*/100ns 70*/100ns 85*/100ns 85*/100ns 85*/100ns
CMOS SRAM
Comments Commercial Extended Industrial Commercial Extended Industrial
* all the AC parameters are measured with 30pF test load
PARAMETER LIST FOR EACH SPEED BIN
Speed Bins Parameter List Read Read cycle time Address access time Chip select to output Output enable to valid output Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Symbol 70ns Min tRC tAA tCO tOE tLZ tOLZ tHZ 70 10 5 0 0 5 70 60 0 60 50 0 0 50 0 5 Max 70 70 35 30 30 25 85 10 5 0 0 10 85 70 0 70 60 0 0 60 0 10 85ns Min Max 85 85 40 35 35 25 100ns Min 100 10 5 0 0 15 100 70 0 70 60 0 0 60 0 10 Max 100 100 50 35 35 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
tOHZ Output hold from address change tOH Write Write cycle time tWC Chip select to end of write tCW Address set-up time Address valid to end of write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tAS tAW tWP tWR tWHZ tDW tDH tOW
-5ELECTRONICS
Revision 04 April 1996
KM62V256C, KM62U256C Family
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Vdr Idr KM62V256CL-L KM62U256CL-L KM62V256CLE-L KM62U256CLE-L KM62V256CLI-L KM62U256CLI-L Data retention set-up time tSDR Recovery time tRDR See data retention waveform Symbol Test Condition* /CS A cc-0.2V V Vcc=3.0V /CS A cc-0.2V V Min 2.0 0 5
CMOS SRAM
Typ** Max 1 0.6 1 0.6 1 0.6 3.6 8 8 10 10 10 10 -
Unit V
uA
ms
* 1) Commercial Product : Ta=0 to 70 C, unless otherwise specified 2) Extended Product : Ta=-25 to 85 C, unless otherwise specified 3) Industrial Product : Ta=-40 to 85 C, unless otherwise specified ** Ta=25 C
DATA RETENTION TIMING DIAGRAM
tSDR Data retention mode tRDR
Vcc 3.0/2.7V* 2.2V Vdr /CS GND
/CS A cc-0.2V V
* 3.0V for KM62V256C family, 2.7V for KM62U256C family
FUNCTIONAL DESCRIPTION
/CS H L L L /WE X H H L /OE X H L X Mode Power Down Output Disable Read Write I/O Pin High-Z High-Z Dout Din Current Mode Isb, Isb1 Icc Icc Icc
-6ELECTRONICS
Revision 04 April 1996
KM62V256C, KM62U256C Family
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE (1)
(/CS=/OE=Vil, /WE=Vih)
tRC Address tAA tOH Data Out Previous Data Valid Data Valid (Address Controlled)
CMOS SRAM
TIMING WAVEFORM OF READ CYCLE
(/WE= VIH ) t RC
Address tAA tCO /CS tHZ t OE /OE tOLZ(4) t LZ Data out High - Z Data Valid tOHZ tOH
Notes (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, HZ (max.) is less than tLZ(min.) both for a given device and from t device to device.
-7ELECTRONICS
Revision 04 April 1996
KM62V256C, KM62U256C Family
TIMING WAVEFORM OF WRITE CYCLE
Address tCW(2) /CS tAW tWP(1) /WE tAS Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH (/WE Controlled) tWC
CMOS SRAM
tWR(4)
TIMING WAVEFORM OF WRITE CYCLE
Address tAS /CS
(/CS Controlled) tWC
tCW(2)
tWR(4)
tAW tWP(1) /WE tDW Data in Data Valid t DH
Data out
High - Z
High - Z
Notes (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of a low /CS and low /WE. A write begins at the latest transition among /CS going low and /WE going low : A write end at the earliest transition among /CS going high and /WE going high, tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS, or /WE going high.
-8ELECTRONICS
Revision 04 April 1996
KM62V256C, KM62U256C Family
PACKAGE DIMENSION
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I
13.40 0.10 (0.528 0.008)
CMOS SRAM
Unit : Millimeters (Inches)
( 0813.4F )
1.20 Max. 0.047 0.00 Min. 0.000 #28 0.20 -0.05
+0.10
#1
+0.004 (0.008) -0.002
8.40 Max. 0.331
0.55 (0.022)
#14
#15
8
AE
11.80 0.10 (0.465 0.004)
0.15 -0.05 0.006
+0.10
+0.004 -0.002
0~
0.50 0.10 0.020 0.004
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I
13.40 0.10 (0.528 0.008)
( 0813.4R )
0.10Max.
0.004Max.
#14
#15
0.20 -0.05
+0.10
+0.004 (0.008) -0.002
8.00 0.315
0.43 0.017
1.20 Max. 0.047 0.00 Min. 0.000
8.40 Max. 0.331
0.55 (0.022)
#1
#28
8
AE
11.80 0.10 (0.465 0.004)
0.15 -0.05 0.006
+0.10
+0.004 -0.002
0~
0.50 0.10 0.020 0.004
0.10Max.
0.004Max.
8.00 0.315
0.43 0.017
-9ELECTRONICS
Revision 04 April 1996
KM62V256C, KM62U256C Family
28 PIN PLASTIC SMALL OUTLINE PACKAGE
(450mil )
CMOS SRAM
0 ~ 8
#28 #15
1.02 0.20 0.040 0.008
8.38 0.20 0.330 0.008
11.81 0.30 0.465 0.012
#1
#14
1.27 0.050
+ 0.10 - 0.05 + 0.004 0.006 - 0.002
0.15
18.69 MAX 0.736 18.29 0.20 0.720 0.008
2.59 0.20 0.102 0.008 3.00 MAX 0.118 0.05 MIN 0.002
0.10 MAX 0.004
0.89 0.035
0.41 0.10 0.016 0.004
- 10 ELECTRONICS
Revision 04 April 1996
KM62V256C, KM62U256C Family
TECHNICAL INFORMATION
1) Icc2 characteristics by temperature variation
CMOS SRAM
All the values in this graph are depicted by the relative value with the maximum value measured at 3.3V Vcc and -40 Ctemperature. The basic relative value of Icc2 at that condition is set into 1.
Icc2 v.s Temperature 1.000 0.900 0.800 0.700 0.600 0.500 -40 -10 0 25 40 70 85 Temerature( E ) 3.0V Device 3.3V Device
2) Isb1(CMOS Level Standby Current) characteristics by temperature variation All the values in this graph are depicted by the relative value with the maximum value measured at 3.0V Vcc and 85 Ctemperature. The basic relative value of Isb1 at that condition is set into 1.
Icc2(Relative Value)
Isb1 v.s Temperature 1.00 0.80 0.60 0.40 0.20 0.00 -40 -10 0 25 40 70 85 Temperature( E ) 2.7V 3.0V
Isb1(Relative Value)
- 11 ELECTRONICS
Revision 04 April 1996
KM62V256C, KM62U256C Family
3) Idr(Data Retention Current) characteristics by temperature variation
CMOS SRAM
All the values in this graph are depicted by the relative value with the maximum value measured at Vdr=3.0V and 85 Ctemperature. The basic relative value of Idr at that condition is set into 1.
Idr v.s Temperature @ Vcc=3.0V 1.00 Idr(Relative Value) 0.80 0.60 0.40 0.20 0.00 -40 -10 0 25 40 70 85 Temperature( E )
- 12 ELECTRONICS
Revision 04 April 1996

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